1. Field of the Invention
The invention relates to a content addressable memory cell having a first memory cell for storing data, the first memory cell being electrically connected to a first bit line pair for transferring the data from and to the first memory cell and to a comparator unit.
2. Description of the Related Art
Content addressable memory (CAM) cells are often used in integrated circuits. CAMs are memories which, besides read and write accesses, also make it possible to search for an entry. During a search, a search word is compared with a set of stored data. The status of whether the search word corresponds to the stored word is indicated for each stored word. An essential feature of a CAM is that each stored word is identified on the basis of the content of the word itself, instead of by its address in the memory arrangement, as is the case with customary digital memories.
A CAM comprises an arrangement or an array of memory cells that are generally arranged in a matrix made of rows and columns. Each memory cell stores an individual bit of digital information. The bits stored in a row or series of memory elements form a stored word. During an adjusting or hit operation, each search word of the input data is applied to all the rows and, for each row, an indication of whether the word sought corresponds to the word stored therein is generated.
Content addressable memory cells may be designed as binary or ternary CAMs. A binary CAM can store two information states, a logic first (“1”) and a logic second (“0”) state. Binary CAMs typically have a RAM (random access memory) cell and a comparator unit. The comparator unit compares the comparison data with data that are stored in the RAM cell array and controls an adjusting line during an adjustment with regard to a predefined state. The columns of a binary CAM can generally be masked with external mask data that are stored in one or a plurality of mask registers.
Ternary CAMs are memory chips that can store three states, namely a first logic state, a second logic state and also a so-called “don't care” state for comparison operations. Ternary CAMs generally have in addition to the first RAM cell array also a second RAM cell array or a second RAM cell that stores local mask data for each CAM cell. By way of example, an Ethernet router stores connection data which indicate to the router what IP (Internet Protocol) addresses are allocated to what ports and are forwarded. In this case, the IP addresses are stored within a CAM cell array. If an IP data packet is transferred, a search is made for this IP address in the CAM cell array. If this IP address is found and the adjusting line is activated, the latter then drives a RAM cell array in which this port number is stored. However, generally use is made not of complete IP addresses but rather merely of parts thereof which, in turn, then describe a specific area of a network. For this purpose, so-called network masks are defined which state which bits of an IP address must correspond in order that the IP address is associated with a network. The problem here is that the mask is not identical for all network areas and must be stored. This means for the CAM cell array that each individual bit of the IP address stored there must be individually masked and the CAN cell array must store the masking information directly with each bit of the IP address. Especially, since new chip architectures are intended to be configurable for a plurality of protocols, the mask functionality must be able to be altered between the individual applications (i.e., the mask functionality must be programmable).
A further exemplary application of essentially binary CAMs is afforded by cache memories of processors. The cache memories enable a CPU (central processing unit) to effect a faster data access than in the case of an external RAM. A cache memory always stores the present data or the data processed last, since the probability of the latter being subjected to further processing is relatively high. Since the stored address areas continually change, the associated address word is always stored with respect to each data word. A search is then made for the address word sought by means of the CAM, and the associated found data word is output.
A conventional CAM cell is illustrated in FIG. 1. The CAM cell has an adjusting or hit logic unit 102 as known in the prior art. Each CAM cell stores a data bit within a stored word. In the CAM cell, a memory cell 101 comprises two inverters 101a and 101b, which are connected in the form of a flip-flop. FIG. 2 shows a conventional realization of the flip-flop with two n-type transistors 201b and 201d and two p-type transistors 201a and the 201c. The flip-flop has two states. The signal “a” is high in one state and low in the other state. The signal “b” is always the complement of “a”. Bit lines BL and BLQ are connected to the memory cell 101 via access gates, illustrated here as transistors 103 and 104. A word line WL is connected to the gate terminal of each access transistor and extends outward to other cells in the same word row. The adjusting logic unit 102 is connected to the memory cell and to the bit lines. Said adjusting logic unit 102 comprises an output, which is designated by MV and indicates the presence of a correspondence.
The operation of the conventional CAM of FIG. 1 is described below. The bit lines BL and BLQ have two functions. Firstly a read/write function and secondly an adjusting or hit function. To perform a read/write function, the word line WL is used to activate the access transistors 103 and 104. An electrical connection is thus produced between the bit lines BL and BLQ and the two terminals of the memory cell 101. As soon as said connection has been produced, the bit lines can either read the state of the memory cell 101 or write a state to the cell.
If the access transistors 103 and 104 are deactivated, the memory cell 101 is isolated from the two bit lines BL and BLQ. In this case, BL and BLQ can be used for their adjusting function. A state is set onto one of the bit lines. If the state of BLQ corresponds to the state of the signal “a”, the MV signal is floating. If it has no correspondence, then MV is pulled low. For example, assuming that the intention is to check whether “a” is high and that a high signal is put onto the line BLQ and a low signal is put onto BL. If “a” is high, the transistor 102b is on whereas the transistor 102a is off (since BL is low), and the transistor 102d is off (because “b” is low) whereas the transistor 102c is on, since a high signal is present on BLQ. MV is thus floating and thereby indicates a correspondence. If “a” is low, the transistors 102b and 102a are off and the transistors 102d and 102c are on (because both BLQ and “b” are high). MV is thus pulled to a low state, thereby indicating no correspondence.
It is therefore evident that when the access transistors 103 and 104 are off and the memory cell 101 is isolated from the bit lines BL and BLQ, the adjusting logic unit 102 can be used to check correspondences between the bit lines and the stored data in the cell.
In the search for correspondences in a CAM, it is known in the prior art to specify the search word, “don't care” in one or more bits. This specification “don't care” means that the CAM cell is to indicate a correspondence independently of the state of its stored bit. A technique for specifying “don't care” in the search word is provided by pulling both the bit line BL and BLQ to a low state.
The technique of specifying “don't care” in the search word is useful only for searching word ranges. For example, to search for all words which lie in the range 1011000 and 1011111, it is possible to specify the search word 1011XXX (where X represents “don't care”). This search word would correspond to all words which fall within the range. This technique can generally be used only for continuous word ranges. By contrast, discontinuous ranges require a plurality of search words.
Particularly when CAMs are used in smart card applications, the embodiment of a CAM with floating nodes is disadvantageous since an unauthorized access can be prevented only to an inadequate extent. Similarly, this relatively poor protection against unauthorized access is afforded in the case of binary CAMs which are not completely constructed from static gates and/or operate with reduced levels.
A CAM cell constructed from six transistors is disclosed in the patent specification U.S. Pat. No. 6,101,116. The CAM cell has an SRAM (static random access memory) cell constructed from a pair of feedback inverters and two access transistors. The SRAM cell stores a data value at an output node at one of the two inverters and an inverse data value at an output node of the other inverter. The two access transistors are in each case connected between an output node and an adjusting line. The adjusting line is connected via the access transistors in such a way that the adjusting line is electrically connected to the output nodes of the SRAM cell if the access transistors are switched on. Data lines are electrically connected to the gate terminals of the access transistors.
A further CAM component specifically embodied as a ternary CAM is disclosed in the patent specification U.S. Pat. No. 6,154,384. The CAM cell has a first memory cell, which is embodied as a RAM cell with two access transistors and two inverters. This first RAM cell is electrically connected to a word line, to a bit line pair, and to a comparator unit. The comparator unit has three transistors, two transistors being electrically connected to a comparison signal line pair and by their gate terminals to the first memory cell. The third transistor produces an electrical connection to a masking circuit formed by a transistor. This transistor has a further connection to an adjusting line. The masking circuit is electrically connected to a masking memory cell constructed as a second RAM cell with two access transistors and two inverters. The access transistors are connected by their gate terminals to a masking word line and in each case by a further terminal to a bit line of the bit line pair.
In the case of the binary CAMs, it is not possible to alter the external mask functionality between the individual applications, i.e., the mask functionality is only one-time programmable, since the comparison algorithm by means of which a search word is compared with the stored comparison words is defined in the semiconductor component and can thus no longer be altered subsequently. In the case of the ternary CAMs, the mask functionality is reconfigurable by means of write operations.
Therefore, there is a need for a content addressable memory cell which can be used to achieve an improved functionality as well as an improved protection against unauthorized access to stored data.